GenArch: gen_lc3b_arch.py

#! /usr/bin/env python2.4
# Yasm LC-3b Architecture Generator
# $Id$
#
#  Copyright (C) 2006  Peter Johnson
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND OTHER CONTRIBUTORS ``AS IS''
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR OTHER CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.

from gen_arch import *

config_arch(lsb_bit = 0,
            insn_bit_width = 16,
            machines = ["lc3b"],
            parsers = ["nasm"])

#
# Registers
#

for x in range(8):
    add_register("r%d" % x, None, x)

#
# Fields
#

add_field("opcode", width=4, lsb=12)
add_field("jsrop", width=1, lsb=11)
add_field("arithop", width=1, lsb=5)
add_field("DR", width=3, lsb=9)
add_field("SR1", width=3, lsb=6)
add_field("SR2", width=3, lsb=0)
add_field("imm5", width=5, lsb=0, signed=True)
add_field("PCoffset9", width=9, lsb=0, rshift=1, pc_rel=True, save="imm")
add_field("PCoffset11", width=11, lsb=0, rshift=1, pc_rel=True, save="imm")
add_field("offset6", width=6, lsb=0, rshift=1, signed=True, save="imm")
add_field("boffset6", width=6, lsb=0, signed=True, save="imm")
add_field("shiftArith", width=1, lsb=5)
add_field("shiftDir", width=1, lsb=4)
add_field("imm4", width=4, lsb=0)
add_field("trapvect8", width=8, lsb=0, rshift=1)

#
# Instructions
#

add_insn("add", "Addition (register)",
         ["DR", "SR1", "SR2"],
         ["reg", "reg", "reg"],
         dict(opcode=0x1, arithop=0))

add_insn("add", "Addition (immediate)",
         ["DR", "SR1", "imm5"],
         ["reg", "reg", "imm"],
         dict(opcode=0x1, arithop=1))

add_insn("and", "Bitwise logical AND (register)",
         ["DR", "SR1", "SR2"],
         ["reg", "reg", "reg"],
         dict(opcode=0x5, arithop=0))

add_insn("and", "Bitwise logical AND (immediate)",
         ["DR", "SR1", "imm5"],
         ["reg", "reg", "imm"],
         dict(opcode=0x5, arithop=1))

add_insn("br", "Conditional branch",
         ["PCoffset9"],
         ["imm"],
         dict(opcode=0, DR=0x7))

add_derived_insn("brp", "br", fields_fixed = dict(opcode=0, DR=0x1))
add_derived_insn("brz", "br", fields_fixed = dict(opcode=0, DR=0x2))
add_derived_insn("brzp", "br", fields_fixed = dict(opcode=0, DR=0x3))
add_derived_insn("brn", "br", fields_fixed = dict(opcode=0, DR=0x4))
add_derived_insn("brnp", "br", fields_fixed = dict(opcode=0, DR=0x5))
add_derived_insn("brnz", "br", fields_fixed = dict(opcode=0, DR=0x6))
add_derived_insn("brnzp", "br", fields_fixed = dict(opcode=0, DR=0x7))

add_insn("jmp", "Jump",
         ["BaseR"],
         ["reg"],
         dict(opcode=0xC),
         dict(SR1="BaseR"))

add_insn("jsr", "Jump to subroutine",
         ["PCoffset11"],
         ["imm"],
         dict(opcode=0x4, jsrop=1))

add_insn("jsrr", "Jump to subroutine",
         ["BaseR"],
         ["reg"],
         dict(opcode=0x4, jsrop=0),
         dict(SR1="BaseR"))

add_insn("ldb", "Load byte",
         ["DR", "BaseR", "boffset6"],
         ["reg", "reg", "imm"],
         dict(opcode=0x2),
         dict(DR="DR", SR1="BaseR", boffset6="boffset6"))

add_insn("ldi", "Load word indirect",
         ["DR", "BaseR", "offset6"],
         ["reg", "reg", "imm"],
         dict(opcode=0xA),
         dict(DR="DR", SR1="BaseR", offset6="offset6"))

add_insn("ldr", "Load word",
         ["DR", "BaseR", "offset6"],
         ["reg", "reg", "imm"],
         dict(opcode=0x6),
         dict(DR="DR", SR1="BaseR", offset6="offset6"))

add_insn("lea", "Load effective address",
         ["DR", "PCoffset9"],
         ["reg", "imm"],
         dict(opcode=0xE))

add_insn("not", "Bitwise complement",
         ["DR", "SR"],
         ["reg", "reg"],
         dict(opcode=0x9, offset6=-1),
         dict(DR="DR", SR1="SR"))

add_insn("ret", "Return from subroutine", [], [],
         dict(opcode=0xC, DR=0, SR1=7, offset6=0))

add_insn("rti", "Return from interrupt", [], [], dict(opcode=0x8))

add_insn("lshf", "Left shift",
         ["DR", "SR", "imm4"],
         ["reg", "reg", "imm"],
         dict(opcode=0xD, shiftArith=0, shiftDir=0),
         dict(DR="DR", SR1="SR", imm4="imm4"))

add_insn("rshf", "Right shift logical",
         ["DR", "SR", "imm4"],
         ["reg", "reg", "imm"],
         dict(opcode=0xD, shiftArith=0, shiftDir=1),
         dict(DR="DR", SR1="SR", imm4="imm4"))

add_insn("rshfa", "Right shift arithmetic",
         ["DR", "SR", "imm4"],
         ["reg", "reg", "imm"],
         dict(opcode=0xD, shiftArith=1, shiftDir=1),
         dict(DR="DR", SR1="SR", imm4="imm4"))

add_insn("stb", "Store byte",
         ["SR", "BaseR", "boffset6"],
         ["reg", "reg", "imm"],
         dict(opcode=0x3),
         dict(DR="SR", SR1="BaseR", boffset6="boffset6"))

add_insn("sti", "Store word indirect",
         ["SR", "BaseR", "offset6"],
         ["reg", "reg", "imm"],
         dict(opcode=0xB),
         dict(DR="SR", SR1="BaseR", offset6="offset6"))

add_insn("str", "Store word",
         ["SR", "BaseR", "offset6"],
         ["reg", "reg", "imm"],
         dict(opcode=0x7),
         dict(DR="SR", SR1="BaseR", offset6="offset6"))

add_insn("trap", "System call", ["trapvect8"], ["imm"], dict(opcode=0xF))

if __name__ == "__main__":
    gen_code("lc3b")