Ticket #119 (closed defect: fixed)

Opened 8 months ago

Last modified 1 month ago

ADDSD instruction is mis-implemented

Reported by: wml@alum.rpi.edu Assigned to:
Priority: P1 Milestone:
Component: Architecture: x86 Version: 0.6.0
Severity: normal Keywords: addsd, x86
Cc:

Description

According to Intel (in the Architecture Manual), the ADDSD instruction takes an XMM register as the destination operand (op 1) and another XMM register or a pointer to a 64-bit memory location in the source operand (op 2). Yasm, right now, will take an XMM register or a 128-bit memory pointer for op 2.

Attachments

Change History

11/27/07 23:21:10 changed by peter

  • status changed from new to closed.
  • resolution set to fixed.

(In [2015]) Fix #119. Quite a few SSE/SSE2 instructions assumed 128-bit memory sizes instead of the correct 64-bit or 32-bit sizes (e.g. xmm/m64 or similar). It worked fine when no memory size was specified, but it should also work with the correct size modifier.

11/28/07 07:32:27 changed by wml@alum.rpi.edu

Great! Thanks muchly.

Add/Change #119 (ADDSD instruction is mis-implemented)