Assembler generates extra opcodes

[michaelryan@…]

For this AMD64 program:
	[BITS 64]
        [SECTION .text] 
	global main
main:
;
; Standard entry linkage
;
	push	rbp
	mov	rbp,rsp
	push	rbx
	push	rsi
	push	rdi
	
        push    QWORD Hello
	add	rsp,8
;
; Standard return linkage
;
	pop	rdi
	pop	rsi
	pop	rbx
	mov	rsp,rbp
	pop	rbp
	xor	rax,rax
	ret
	[SECTION .data]
Hello:  db	'Hello, World',10,0

this is the generated code:

Dump of assembler code for function main:
    0x00000000004004c0 <main+0>:    push   %rbp
    0x00000000004004c1 <main+1>:    mov    %rsp,%rbp
    0x00000000004004c4 <main+4>:    push   %rbx
    0x00000000004004c5 <main+5>:    push   %rsi
    0x00000000004004c6 <main+6>:    push   %rdi
    0x00000000004004c7 <main+7>:    pushq  $0x500690
    0x00000000004004cc <main+12>:   add    %al,(%rax)
    0x00000000004004ce <main+14>:   add    %al,(%rax)
    0x00000000004004d0 <main+16>:   add    $0x8,%rsp
    0x00000000004004d7 <main+23>:   pop    %rdi
    0x00000000004004d8 <main+24>:   pop    %rsi
    0x00000000004004d9 <main+25>:   pop    %rbx
    0x00000000004004da <main+26>:   mov    %rbp,%rsp
    0x00000000004004dd <main+29>:   pop    %rbp
    0x00000000004004de <main+30>:   xor    %rax,%rax
    0x00000000004004e1 <main+33>:   retq

The opcodes at 4004cc and 4004ce do not appear in the source.

[mu@…]

This looks like a bug in objdump (and whatever you used) to me.  I just tried
this and the relevant lines:
   7:   68 00 00 00 00          pushq  $0x0
                        8: R_X86_64_64  .data
   c:   00 00                   add    %al,(%rax)
   e:   00 00                   add    %al,(%rax)
together add up to a 64bit constant.  Peter's the local expert, as it were, and
if it is a bug in yasm it's probably in the amd64 core, not ELF (I see the
equivalent bytes in -fbin). In case I'm wrong and this actually is a generation
bug and is specific to ELF, just throw it right back at me, Pete.

[peter@…]

Fixed in modules/arch/x86/x86id.re r1.66.

The push instruction in AMD64 takes a signed 32-bit immediate.  Trying to follow
the NASM path, I'm making push take a DWORD rather than a QWORD, so the new
syntax will be "push DWORD Hello".  While this seems somewhat confusing, the
same thing happens with "push BYTE 0".  Note there is no 32-bit push in 64-bit
mode; there's only a 64-bit push that takes a 32-bit immediate value.

Interestingly, Intel's IA-32e documentation states push takes an /unsigned/
32-bit immediate (e.g. it's zero-extended rather than sign-extended).  I hope
this is a typo, for everyone's sake.

Thanks for the bug report!